Power management, to improve the power efficiency of Micro Processing Unit (MPUs), Field Programmable Gate Array (FPGAs) and Digital Signal Processor (DSPs) and the like, has become a vital element in digital system design. The power management system includes a full operation mode, standby mode, and sleep mode. The clock frequency, core voltage and/or core current are changed in each mode accordingly. As a result, the output current of the Point-Of-Load (POL) DC-DC converters is intermittent and has a high slew rate. A low output voltage, a large output current and a high speed response are required for the POL. In such a condition, control circuits with high accuracy and high-speed are required as the tolerance of the output voltage becomes internally severe for speed and lower voltage of the Micro Processor Units (MPUs), Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). A general control method is pulse width modulation (PWM) control with Proportional Integral Derivative (PID). Generally, such control circuits are composed with analog circuits and/or simple combination digital circuits.
Robustness or flexible controls for versatile conditions are demanded which cannot be accomplished with analog control circuits. For the control purpose, DPWM control is a one of appropriate technique. Also current analog comparator methods for pulse width modulation are not programmable and may not be calibrated.
DPWM have technical limitations mainly associated with delay related with the sampling process and discrete-time computation. There is generally a tradeoff between the sampling and computation frequency, and the controller power use. Thus, it is beneficial to develop specialized analog-to-digital converter (ADC) architectures which can meet the voltage regulation requirements without excessive power consumption. Importantly, applications requiring very high speed of response (of order of 100 ns) tend to be high-power applications such as servers, where the power overhead of a fast, high-resolution ADC's is negligible.
DPWM requires high resolution to produce tightly regulated output voltages, and for elimination of undesirable limit-cycle oscillations of output voltage and inductor current, thus may not be able to provide real time calibration.
A need therefore exists for a high resolution DPWM with continuous real time calibration.